DEFINITY Enterprise Communications Server Release 7
Maintenance for R7r
555-230-126
Issue 4
June 1999
Maintenance Object Repair Procedures
9-1345PROCR (RISC Processor Circuit Pack)
9
Error Log Entries and Test to Clear Values
Notes:
a. This error (150) indicates that a SPE interchange has occurred and that
the Processor circuit pack was the cause of the spontaneous interchange.
1. If other PROCR errors are present, investigate these errors.
2. If no other PROCR errors are present, run the
test processor a|b
long clear
command and investigate any test failures.
b. A parity error was detected in the processor’s data cache or instruction
cache. In a system with duplicated SPEs, this error can be generated only
while the processor is running on the active SPE since the software
running on the standby processor does not use the Processor data and
instruction caches. Therefore, if PROC error 1026 is present for a
processor on the standby SPE, that error must have been generated some
time in the past when the processor was running as the active SPE.
Execute the test processor long command for a processor either on the
active or standby SPE, and if any tests fail, follow the repair procedures for
those failures. It is unlikely that a parity error will occur at the time the
Table 9-527. PROCR Error Log Entries
Error
Type
Aux
Data Associated Test
Alarm
Level
On/Off
Board Test to Clear Value
0
1
1. Run the Short Test Sequence first. If all tests pass, run the Long Test Sequence. Refer to the
appropriate test description and follow the recommended procedures.
0 Any Any Any test processor UUC s r 1
1 BOOTPROM Checksum
Test (#897)
MAJOR
2
2. If a spontaneous interchange has occurred (as indicated by STBY-SPE error type 103 or the display
init causes screen), and handshake is down, (check with status spe), replace the alarmed circuit
pack on the standby SPE. If handshake is up, execute a test long clear of the alarmed circuit pack
and follow recommended procedures.
ON test processor UUC s r 1
150(a) Any None MAJOR† ON test processor UUC l c
257 Parity Checker Test
(#899)
MINOR ON test processor UUC s r 2
513 Write Buffer Test (#900) MAJOR† ON test processor UUC s r 1
1025 Cache Audit (#896) MINOR ON test processor UUC s r 2
1026(b) Cache Audit (#896) MAJOR ON test processor UUC s r 2
1281 Cache Test (#895) MAJOR† ON test processor UUC l r 1
