DEFINITY Enterprise Communications Server Release 7
Maintenance for R7r
555-230-126
Issue 4
June 1999
Maintenance Object Repair Procedures
9-1027MEM-BD (32MB Memory Circuit Pack)
9
Processor) on Memory reads. If the parity checking logic fails, it will either
generate errors when it shouldn’t (a serious error condition that will probable
result in SPE Down) or miss errors when present (less serious).
The burst read circuit supports a special, block read mode used by the
Processor to quickly load program instructions into the Processor cache. Given a
single starting address over the Processor Bus, the Memory transfers four words
of data back to the Processor. This reduces the time it takes for the Processor to
get instructions. Problems in this circuit may be due to the Memory circuit pack
or Processor and will result in SPE Down.
If the PBX system is equipped with High Reliability or Critical Reliability option
(i.e. with duplicated SPEs), and if a failure of the active Memory circuit pack
causes a MAJOR on-board alarm, a SPE interchange will occur if the health of
the standby SPE permits the interchange.
