EM78P221/2N
8-Bit Microcontroller with OTP ROM
22 •
Product Specification (V1.0) 10.19.2007
(This specification is subject to change without further notice)
6.3 TCC/WDT and Prescaler
There are two 8-bit counters available as prescalers for the TCC and WDT. The
PST0~PST2 bits of the CONT register are used to determine the ratio of the TCC
prescaler, and the PWR0~PWR2 bits of the Bank 1-RE register are used to determine
the WDT prescaler. The prescaler counter is cleared by the instructions each time
such instructions are written into TCC. The WDT and prescaler are cleared by the
“WDTC” and “SLEP” instructions. Fig. 6-2 depicts the block diagram of TCC/WDT.
TCC (Bank 3-R5) is an 8-bit timer/counter. The TCC clock source can be internal clock
(Fosc) or external signal input (edge selectable from the TCC pin). If the TCC signal
source is from an external clock input, TCC will be incremented by 1 at every falling
edge or rising edge of the TCC pin. The TCC pin input time length (kept at High or Low
level) must be greater than 1CLK. 1 CLK is always Fosc/2..Refer to Fig. 6-2.
NOTE
The internal TCC will stop running when in sleep mode.
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on
running even when the oscillator driver has been turned off (i.e., in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled at any time during normal mode
through software programming. Refer to WDTE bit of Bank 1-RE register (Section
6.2.10 Bank 1-RE (WDT Control Register). With no prescaler, the WDT time-out
duration is approximately 18ms.
1
1
VDD=5V, WDT Time-out period = 15.2ms ± 30%.
VDD=3V, WDT Time-out period = 18ms ± 30%.
