EM78P221/2N
8-Bit Microcontroller with OTP ROM
Product Specification (V1.0) 10.19.2007 • 9
(This specification is subject to change without further notice)
6.2.3 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to perform as an
indirect address pointer. Any instruction using R0 as a pointer, actually accesses the
data pointed by the RAM Select Register (R4).
6.2.4 R1 (Memory Switch Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
“0” “0” “0” “0” “0” “0” BS1 BS0
Bits 7~2: not used bits, fixed to 0 all the time.
Bits 1~0: used to select Banks 0 ~ 3 for R20~R3F and select Banks 0 ~ 3 for the
control register.
See the table under Section 6.2 Registers Description for the data memory
configuration.
6.2.5 R2 (Program Counter and Stack)
On-chip Program
Memory
000H
FFFH
008H
Interrupt Vector
User Memory Space
Reset Vector
A11 A10
Stack Level 1
Stack Level 3
Stack Level 2
Stack Level 4
Stack Level 5
CALL
00 PAGE0 0000~03FF
01 PAGE1 0400~07FF
10 PAGE2 0800~0BFF
11 PAGE3 0C00~0FFF
RET
RETL
RETI
A9 ~ A0
Stack Level 6
Stack Level 7
Stack Level 8
R1(5,4)
Fig. 6-1 Program Counter Organization
R2 and hardware stacks are 12-bit wide. The structure is depicted in the table under
Section
6.1 Register Configuration.
Generates 4K×13 bits on-chip ROM addresses to the relative programming instruction
codes. One program page is 1024 words long.
The contents of R2 are all set to "0"s when a reset condition occurs.
