A SERVICE OF

logo

Open as PDF
next previous
19
4173ES–USB–09/07
AT89C5132
6.3 AC Characteristics
6.3.1 External 8-bit Bus Cycles
6.3.1.1 Definition of Symbols
Table 6. External 8-bit Bus Cycles Timing Symbol Definitions
6.3.1.2 Timings
Test conditions: capacitive load on all pins = 50 pF.
Table 7. External 8-bit Bus Cycle – Data Read AC Timings
V
DD
= 2.7 to 3.3V, T
A
= -40° to +85°C
Signals Conditions
A Address H High
D Data In L Low
L ALE V Valid
Q Data Out X No Longer Valid
RRD
ZFloating
WWR
Symbol Parameter
Variable Clock
Standard Mode
Variable Clock
X2 Mode
UnitMin Max Min Max
T
CLCL
Clock Period 50 50 ns
T
LHLL
ALE Pulse Width 2·T
CLCL
-15 T
CLCL
-15 ns
T
AVLL
Address Valid to ALE Low T
CLCL
-20 0.5·T
CLCL
-20 ns
T
LLAX
Address hold after ALE Low T
CLCL
-20 0.5·T
CLCL
-20 ns
T
LLRL
ALE Low to RD Low 3·T
CLCL
-30 1.5·T
CLCL
-30 ns
T
RLRH
RD Pulse Width 6·T
CLCL
-25 3·T
CLCL
-25 ns
T
RHLH
RD high to ALE High T
CLCL
-20 T
CLCL
+20 0.5·T
CLCL
-20 0.5·T
CLCL
+20 ns
T
AVDV
Address Valid to Valid Data In 9·T
CLCL
-65 4.5·T
CLCL
-65 ns
T
AVRL
Address Valid to RD Low 4·T
CLCL
-30 2·T
CLCL
-30 ns
T
RLDV
RD Low to Valid Data 5·T
CLCL
-30 2.5·T
CLCL
-30 ns
T
RLAZ
RD Low to Address Float 0 0 ns
T
RHDX
Data Hold After RD High 0 0 ns
T
RHDZ
Instruction Float After RD High 2·T
CLCL
-25 T
CLCL
-25 ns