AMD 30925 Washer/Dryer User Manual


 
Builder’s Guide for AMD Opteron™ Processor-Based
Servers and Workstations
30925 Rev. 3.04 February 2004
10 AMD Opteron™ Processor Key Architectural Features
Chapter 1
Integrated DDR DRAM Memory Controller
The 128-bit wide integrated DDR DRAM memory controller:
changes the way the processor accesses main memory, resulting in increased bandwidth,
reduced memory latencies, and increased processor performance.
allows available memory bandwidth to scale with the number of processors.
can support up to eight registered DDR DIMMs per processor.
has available memory bandwidth of up to 5.3 Gbytes/s (with PC2700) per processor.
HyperTransport™ Technology
The HyperTransport technology of the AMD64 architecture offers the following features:
A scalable bandwidth interconnection between processors, I/O subsystems, and other chipsets
Support for up to three coherent HyperTransport links, providing up to 19.2 Gbytes/s of peak
bandwidth per processor
Up to 6.4 Gbytes/s bandwidth per link providing sufficient bandwidth for supporting new
interconnects including PCI-X, DDR, InfiniBand, and 10G Ethernet
Low power consumption (1.2 W) to help reduce the system thermal budget
Other Features of the AMD Opteron™ Processor
Other features of the AMD Opteron processor include:
64-bit wide key data and address paths that incorporate a 48-bit virtual address space and a
40-bit physical address space
ECC (error correcting code) protection for L1 cache data, L2 cache data and tags, and DRAM
with hardware scrubbing of all ECC-protected arrays
Lower thermal output levels and improved frequency scaling through .13 micron SOI (silicon-
on-insulator) process technology
Support for all instructions necessary to be fully compatible with SSE2 technology
Two additional pipeline stages (compared to AMD’s 32-bit architecture) for increased
performance and frequency scalability
Higher IPC (instructions-per-clock) achieved through additional key features, such as larger
TLBs (translation lookaside buffer), flush filters, and enhanced branch prediction algorithms