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TMPR3901F
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2.1.2 Address mapping
Address mapping in the TMPR3901F is performed by the direct segment mapping MMU in the R3900
Processor Core. The TMPR3901F uses the kseg2 reserved area (0xFF00 0000 - 0xFFFF FFFF) as
follows.
0xFF00 0000 - 0xFF00 FFFF address protection unit
0xFF20 0000 - 0xFF3F FFFF debug support unit
The TMPR3901F outputs bus operation signals even when it accesses the above area. The
TMPR3901F ignores bus operation input signals (ACK*, BUSERR*, etc) at that time.
2.2 Clock Generator
A quadruple-frequency PLL (phase locked loop) clock is built in and operates with an external crystal
generator. It can be connected to the TMPR3901F internal PLL clock generator and quarter-frequency
crystal oscillator.
The PLL and internal clock can be stopped with an external signal. The TMPR3901F supports a Reduced
Frequency mode to control the clock frequency of the processor core by setting the Config register RF field
(see Chapter 5 for details).