Architecture
90
8.3 Details of Debug Exceptions
(1) Single Step exception
• Cause
− When the Debug register SSt bit is set, a Single Step exception is raised each time one
instruction is executed.
• Exception masking
− The Single Step exception can be masked by the Debug register SSt bit. When SSt is cleared to
0, a Single Step exception cannot be raised.
(Note : In the debug exception handler, a Single Step exception is masked regardless of the SSt
bit value.)
• Processing
− When this exception is raised, processing jumps to a special debug exception handler at 0xBFC0
0200. (In the R3900 Processor Core, the debug exception vector is located in an uncacheable
address space.)
− The DSS bit in the Debug register is set to 1.
− A Single Step exception is not raised for an instruction in the branch delay slot.
− The DEPC register points to the instruction for which a Single Step exception was raised (the
instruction about to be executed).
− When DERET is issued, a Single Step exception is not raised for an instruction at the return
destination. If the return destination instruction is a branch instruction, a Single Step exception
is not raised for that branch instruction or for the instruction in the branch delay slot.
