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Chapter 16 Clock Supervisor
4.Operation Modes
■ Check if reset was asserted by the Clock Supervisor
To find out whether the Clock Supervisor has asserted reset , the software must check the reset cause by reading
the WDTC register at address A8
H
. If ERST (bit 4 of WDTC) is set, the cause was either external reset at the
RSTX pin or the clock supervisor. If neither SM bit nor MM bit (bit 5 and bit 6 of CSVCR) is set, reset cause was
the external reset. If SM is ’1’ the reset cause is a missing sub-clock and if MM is ’1’ the reset cause is a missing
main clock.