1 Hardware Overview 1.2 System Unit Block Diagram
PCI Bus Support
– Supports synchronous / asynchronous clock mode between the processor
bus and the PCI bus
– 32-bit Address / Data PCI bus using PCI bus driver technology
– Supports up to 5 PCI masters excluding the M1672 and PCI-to-ISA bridge
– Parity protection on all PCI bus signals
– Fully supports PCI Configuration Space Enable (CSE) protocol
– Fully compliant with PCI Rev. 2.2
– Supports delayed transaction
– Dynamic memory prefetch algorithm and programmable post write flush
algorithm
– Data Collection/Write assembly of line bursts
– Supports concurrent PCI bus burst transfer at zero wait-states
Trident CyberBlade XP Graphic Core Highly Integrated Graphics Engine
– Advanced CyberBlade XP Dual-Pixel, Quad-Texture Single-Pass 3D
rendering engine
– 128-bit internal bus interface to Core logic block
– Supports Microsoft DirectX 7.0/8.0 with Cubic Mapping
– Integrated Dual-channel LVDS transmitter
– Digital interface to external TMDS transmitter
– Digital interface to external TV encoder
– DVD hardware assist with Motion Compensation (MC) and Inverse
Discrete Cosine Transform (IDCT)
– TrueVideo with Advanced Video De-interlacing
– PC2001 Compliant
Packaging
– 645 balls in 37.5 x 37.5mm BGA package
1-10 Satellite A20 Maintenance Manual (960-444)
