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26
CHAPTER 3 CPU ARCHITECTURE
Figure 3-2. Memory Map (
µ
PD78082)
Data memory
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General Registers
32 × 8 bits
Internal ROM
16384 × 8 bits
CALLF Entry Area
CALLT Table Area
Vector Table Area
Program Area
Program Area
Unusable
Program
memory
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Internal High-speed RAM
384 × 8 bits
Special Function
Registers (SFRs)
256 × 8 bits
FF00H
FEFFH
FEE0H
FEDFH
FD80H
FD7FH
4000H
3FFFH
FFFFH
1000H
0FFFH
0800H
07FFH
0080H
007FH
0040H
003FH
3FFFH
0000H
0000H