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CHAPTER 12 INTERRUPT FUNCTION
12.4.5 Interrupt request reserve
There are some instructions which, though an interrupt request may be generated while they are being executed,
will reserve the acknowledgment of the request until after execution of the next instruction. These instructions (interrupt
request reserve instructions) are shown below.
• MOV PSW, #byte
• MOV A, PSW
• MOV PSW, A
• MOV1 PSW.bit, CY
• MOV1 CY, PSW.bit
• AND1 CY, PSW.bit
• OR1 CY, PSW.bit
• XOR1 CY, PSW.bit
• SET1 PSW.bit
• CLR1 PSW.bit
• RETB
• RETI
• PUSH PSW
• POP PSW
• BT PSW.bit, $addr16
• BF PSW.bit, $addr16
• BTCLR PSW.bit, $addr16
•EI
•DI
• Manipulate instructions for IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, PR1L, INTM0, INTM1 registers
Caution The BRK instruction is not one of the above interrupt request reserve instructions. However in
the case of software interrupts, which are activated by execution of the BRK instruction, the IE
flag is cleared to 0. Therefore, even if a maskable interrupt request is generated during BRK
instruction execution, the interrupt request will not be acknowledged. However, non-maskable
interrupt requests will be acknowledged.
