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70
CHAPTER 5 CLOCK GENERATOR
Figure 5-1. Block Diagram of Clock Generator
Main
System
Clock
Oscillator
X2
X1
STOP
PCC2
PCC1
Internal Bus
Standby
Control
Circuit
2
f
XX
2
2
fXX
2
3
fXX
2
4
fXX
Prescaler
Clock to
Peripheral
Hardware
Prescaler
Oscillation Mode
Selection Register
f
XX
CPU Clock
(f
CPU)
Scaler
Selector
fX
2
f
X
MCS
Processor Clock Control Register
PCC0
3
Selector