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© Copyright IBM Corp. 2001, 2002 9
Chapter 2. Architecture and technical
overview
The following sections provide more detailed information about the architecture of the Models
6C1 and 6E1. Figure 2-1 shows the high level system block diagram of both models.
Figure 2-1 Model 6C1 and 6E1 - high-level system block diagram
2
Integrated Service
Processor
PCIBridge
PCIBridge
External
Ultra3-SCSI
10/100
Ethernet
3rd serial
port
Super
I/O
ISA Bridge
2PCISlots
32bit
33MHz
5v
2PCISlots
64-bit
50 MHz
3.3v
System Planar
Data
Addr/Cntl
MemoryDataBus
Memory
Address
6xxData Bus
6xxAddress Bus
Memory
512 MB- 8 GB
Processor Card
POWER3-II
333MHz,
375 MHz,or
450MHz
4MBL2
w/ 375 MHz
8MBL2
w/ 450 MHz
Processor Card
POWER3-II
4MBL2
w/ 375 MHz
8MBL2
w/ 450 MHz
SCSI Controller
Internal
Ultra3-SCSI
10/100
Ethernet
IDE
CD-
ROM
1PCISlots
64bit
33MHz
5v
16 Bytes @ 93.75 MHzw/ 375 MHz
16 Bytes @ 90.00 MHzw/ 450 MHz
16 Bytes @ 93.75 MHzw/ 375 MHz
16 Bytes @ 90.00 MHzw/ 450 MHz
6xx-MX Bus
66 MHz
250 MHz
w/ 375 MHz
225 MHz
w/ 450 MHz
250 MHz
w/ 375MHz
225 MHz
w/ 450MHz
4MBL2
w/ 333 MHz
4MBL2
w/ 333 MHz
333MHz,
375 MHz,or
450MHz
166.5 MHz
w/ 333 MHz
166.5 MHz
w/ 333MHz
16 Bytes @ 95.14 MHzw/ 333 MHz
16 Bytes @ 95.14 MHzw/ 333 MHz