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DM9161B
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final 42
Version: DM9161B-12-DS-F01
January 31, 2008
9.4.19 RMII Timing Diagram
9.4.20 RMII Timing Parameter
Symbol Parameter Min. Typ. Max. Unit Conditions
Fref REF_CLK Frequency 49.9985 50 50.0015 MHz 30ppm
(1.5KHZ)
Tref% REF_CLK Duty Cycle 35 - 65 %
Tref REF_CLK Clock Cycle 20 - ns 30ppm
Tsu TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RX_ER
Data Setup to REF_CLK rising edge
4 - - ns
Thold TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RX_ER
Data hold from REF_CLK rising edge
2 - - ns
TXD[1:0], TX_EN,
RXD[1:0], CRS_DV,
RX_ER
REF_CLK
Tsu Thold
T
REF